Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - fifo verilog

Search list

[Other resource] simple_fifo

Description: verilog HDL原码 一种简单的同步FIFO原码，可以被综合-verilog HDL original code a simple synchronous FIFO original code, which can be integrated
Platform: | Size: 1467 | Author: zxz | Hits:

[Embeded-SCM Develop] fifo_datapath

Description: verilog实现，串转并通过fifo再并转串，可以满足输入速率自由输出的一半时，输出仍可持续发送-verilog achieved, and through serial switch and switch again fifo Series, Rate free importation to meet half of the output, the output is still sustainable Send
Platform: | Size: 2427 | Author: seiji | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: 用verilog语言编写的FIFO文件，这是一种传统的按序执行方法，先进入的指令先完成并引退，跟着才执行第二条指令，希望能够帮助读者-With verilog language FIFO file, which is a traditional sequential execution method, first enter the command to finish and retire, followed by only the second instruction execution, hoping to help readers
Platform: | Size: 2048 | Author: huawei | Hits:

[VHDL-FPGA-Verilog] fifo

Description: 异步FIFO的verilog实现，可以参考一下-Verilog asynchronous FIFO implementation, you can refer to
Platform: | Size: 51200 | Author: kobe | Hits:

[Mathimatics-Numerical algorithms] SOA_MAT

Description: VERILOG code for NOC FIFO -VERILOG code for NOC FIFO ..
Platform: | Size: 515072 | Author: praveen | Hits:

[VHDL-FPGA-Verilog] fifofinal

Description: FIFO verilog学习时的基础编程练习。以8位输入，8位输出为例，输入输出采取不同时钟。 附加testbench。-first in first out
Platform: | Size: 2048 | Author: 刘思晗 | Hits:

[LabView] SDRAM-and-FIFO-for-DE1-SoC-master

Description: Verilog TUTORIAL for beginners. We had earlier published a Verilog tutorial that made use of the Xilinx ISE Simulator.
Platform: | Size: 11482112 | Author: kimluan | Hits:

[VHDL-FPGA-Verilog] [verilog]dcfifo_256x32

Description: Dual-Clock FIFO, Depth: 256 Width: 32 USEDW: Y FULLL:Y EMPTY:Y-This is self-defined Dual-Clock FIFO, using logic lut resources.
Platform: | Size: 1024 | Author: ylwang | Hits:

[VHDL-FPGA-Verilog] FIFO_RAM

Description: 同步FIFO_RAM的设计及其testbench(8 bit SYN FIFO module fifo_v(clk,rst,wen,ren,full,empty,data,q);)
Platform: | Size: 3072 | Author: 炜仔mjw | Hits:

[VHDL-FPGA-Verilog] FIFO_ASY

Description: 异步FIFO，利用格雷码作异步FIFO指针减少亚稳态产生，利用同步寄存器放置亚稳态的级联传播。(Asynchronous FIFO, using gray code for asynchronous FIFO pointer to reduce metastable, cascade propagation using synchronous register placed metastable.)
Platform: | Size: 2048 | Author: 253765952 | Hits:

[VHDL-FPGA-Verilog] 带FIFO的ov7670 FPGA应用程序，经测试可用

Description: 这是用Verilog编写的OV7670摄像头驱动代码，带FIFO，经测试可用。(This is written in Verilog OV7670 camera driver code, with FIFO, tested available.)
Platform: | Size: 1683456 | Author: jomair | Hits:

[VHDL-FPGA-Verilog] sdtest

Description: 这个是一个verilog程序，可以用spi读取sd卡中的内容，存到fifo中(This project can read the data from SD card through SPI interface and store the data in FIFO.)
Platform: | Size: 13569024 | Author: jyc | Hits:

[VHDL-FPGA-Verilog] fifo_controller

Description: 用verilog语言实现FIFO控制器，控制FIFO的读写过程，有空满标志(Implementing the FIFO controller)
Platform: | Size: 84992 | Author: 牛啊你 | Hits:

[VHDL-FPGA-Verilog] sfifo

Description: fifo 控制器，也是转载的，主要是为了积分(A fifo controller verilog description.)
Platform: | Size: 1024 | Author: 123yyy | Hits:

[Other] uart_fifo_n

Description: verilog 带fifo的串口收发模块(verilog uart with fifo)
Platform: | Size: 7583744 | Author: yxsheron | Hits:

[Com Port] tx_interface_project

Description: 带FIFO的串口发送模块，简单的FPGA串口发送模块(Serial transmission module with FIFO)
Platform: | Size: 850944 | Author: lionel_messi | Hits:

[VHDL-FPGA-Verilog] FPGA_USB2.0设计

Description: 把FX2配置成从FIFO的模式， 配置为单片机工作时钟24M，端点2输出，字节1024，端点6输入，字节1024，信号全设置为低电平有效等。我们的模块驱动时钟我们配置成内部输出时钟，也就是让FX2给我们的设计当做时钟源，输出一个最大的配置时钟48M的时钟。(The FX2 is configured from FIFO mode, configured as MCU working clock 24M, endpoint 2 output, byte 1024, endpoint 6 input, byte 1024, signal all set to low level and so on. Our module drive clock is configured as an internal output clock, that is, let FX2 give our design as the clock source, and output a clock with the largest configuration clock 48M.)
Platform: | Size: 430080 | Author: 硅渣渣 | Hits:

[VHDL-FPGA-Verilog] sobel

Description: 由Verilog编写在FPGA实现sobel算法应用于图像边缘检测，工程文件可在quartus13.1以上版本打开；工程使用到ram、fifo、pll三种ip核，design文件夹下包含ram、fifo、vga控制以及串口收发和sobel算法模块，sim和doc文件夹下分别包含modelsim的仿真模块和仿真结果；测试时将200*200分辨率的图片用matlab文件夹下的matlab脚本压缩、二值化，再将生成文件中数据用串口发给FPGA，边缘检测结果会通过VGA输出。(Written by Verilog in the FPGA implementation sobel algorithm applied to the edge detection of the image, the project file can be opened in the quartus13.1 or later project use ram, fifo, pll three ip kernel, design folder contains ram, fifo, vga control and Serial port transceiver and sobel algorithm module, sim and doc folder, respectively, include modelsim simulation module and simulation results test will be 200* 200 resolution picture matlab folder under the matlab script compression, binarization, and then generated Data in the file with the serial port to the FPGA, edge detection results will be output through the VGA.)
Platform: | Size: 10222592 | Author: 丶大娱乐家 | Hits:

[VHDL-FPGA-Verilog] FIFO_UVM

Description: fifo uvm this is total fifo tb with uvm including score board with total uvm_topology with test cases with rtl giving proper output(this is total fifo tb with uvm including score board with total uvm_topology with test cases with rtl giving proper output)
Platform: | Size: 231424 | Author: gana123 | Hits:

[VHDL-FPGA-Verilog] 通信协议FPGA

Description: 本设计是基于FPGA的高速并行接口通信接口和协议设计，该设计使用的是8 位并行接口，通过配置FPGA的FIFO寄存器保证了在高速并行下的数据稳定性，在 最终的测试中，该协议能够稳定传输的速度为80Mbps。(This design is based on FPGA high-speed parallel interface communication interface and protocol design, the design uses 8 Bit parallel interface ensures the data stability under high-speed parallel by configuring the FIFO register of FPGA. In the final test, the protocol can stably transmit at 80 Mbps.)
Platform: | Size: 19605504 | Author: 蔺娇娇 | Hits:
« 1 2 ... 9 10 11 12 13 1415 16 17 18 19 ... 22 »

CodeBus www.codebus.net